Ted Boydston
Ted Boydston retired from L3Harris as a senior manager responsible for the employees, operations, budgets, and strategic plans of the EDA/ECAD group. As a polymath, Ted successfully transitioned to private investing, using his engineering and management experience to drive returns.
Ted’s demonstrated skill inventory includes: Management: consensus building, employee growth, strategic planning, six-sigma yellow belt Finance: ROi modeling, cost savings, budget control Vendors: relationship management, contract analysis/negotiation, opportunity management Licensing: reporting, optimization, and management of Flexera FlexNet/FlexLM and other minor vendors Engineering: ASIC/FPGA design, tools, methodology, and technology Languages: VHDL, MCL, Bash, Perl, Python, TCL. Design: Sigasi HDT, Siemens/Mentor Visual Elite, EMA Timing Designer, Sublime Text, Nedit, vi Electronic System Level: Synopsys Synphony Model Compiler, MathWorks MATLAB/Simulink Functional Verification: Cadence Denali Memory Models, Cadence Incisive/Xcelium, Real Intent Ascent Lint, Synopsys DesignWare Synthesis: Synopsys Design Compiler (Ultra), Synopsys Module Compiler, Synplify Pro, Synplify Premier Analysis: Synopsys Primetime, Synopsys PrimePower FPGA Implementation: Xilinx (Vivado, ISE), Intel/Altera, Microsemi/Actel, and Lattice Semiconductor ASIC Implementation: Honeywell VDS Toolkit Formal Verification: Synopsys Formality Data Science: NumPy, SciPy, Pandas, Pyomo, Tableau Computing: Linux RHEL, Environment Modules, Univa Grid Engine
Ted’s demonstrated skill inventory includes: Management: consensus building, employee growth, strategic planning, six-sigma yellow belt Finance: ROi modeling, cost savings, budget control Vendors: relationship management, contract analysis/negotiation, opportunity management Licensing: reporting, optimization, and management of Flexera FlexNet/FlexLM and other minor vendors Engineering: ASIC/FPGA design, tools, methodology, and technology Languages: VHDL, MCL, Bash, Perl, Python, TCL. Design: Sigasi HDT, Siemens/Mentor Visual Elite, EMA Timing Designer, Sublime Text, Nedit, vi Electronic System Level: Synopsys Synphony Model Compiler, MathWorks MATLAB/Simulink Functional Verification: Cadence Denali Memory Models, Cadence Incisive/Xcelium, Real Intent Ascent Lint, Synopsys DesignWare Synthesis: Synopsys Design Compiler (Ultra), Synopsys Module Compiler, Synplify Pro, Synplify Premier Analysis: Synopsys Primetime, Synopsys PrimePower FPGA Implementation: Xilinx (Vivado, ISE), Intel/Altera, Microsemi/Actel, and Lattice Semiconductor ASIC Implementation: Honeywell VDS Toolkit Formal Verification: Synopsys Formality Data Science: NumPy, SciPy, Pandas, Pyomo, Tableau Computing: Linux RHEL, Environment Modules, Univa Grid Engine
Country:
US